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An innovative domain strategy and coverage metric for integrated circuit design validation is proposed. The domain strategy generates test points to examine the borders of a domain to detect whether a design fault has occurred, as either one or more of these borders have shifted or else the corresponding predicate relational operator has changed. The domain coverage metric is applied to measure the completeness and quality of the validation approach. The domain strategy and coverage metric have been implemented using VPI (Verilog procedural interface) and have been applied to validation of industry circuits under design. Our domain coverage tool works smoothly with simulator and vector generator. The results showed that the domain strategy is efficient in generating test points, and the domain coverage metric is powerful in finding potential boundary faults.