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Design of sub-90 nm circuits and design methodologies

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5 Author(s)

Summary form only given. The tutorial discusses the design challenges of scaled CMOS circuits in sub-90 nm technologies and the design methodologies required in order to produce robust designs with the desired power-performance trade-off. We focus on four major components: design challenges of sub-90 nm CMOS circuits with particular emphasis on the implications of each individual device scaling element on circuit design; design methodologies for implementing robust circuits with desired power performance characteristics; managing leakage power; circuit design in the presence of uncertainty.

Published in:

Quality of Electronic Design, 2005. ISQED 2005. Sixth International Symposium on

Date of Conference:

21-23 March 2005