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Exploiting prediction to reduce power on buses

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4 Author(s)
Wen, V. ; Comput. Sci. Div., Calfornia Univ., Berkeley, CA, USA ; Whitney, M. ; Patel, Y. ; Kubiatowicz, J.D.

We investigate coding techniques to reduce the energy consumed by on-chip buses in a microprocessor. We explore several simple coding schemes and simulate them using a modified SimpleScalar simulator and SPEC benchmarks. We show an average of 35% savings in transitions on internal buses. To quantify actual power savings, we design a dictionary based encoder/decoder circuit in a 0.13 μm process, extract it as a netlist, and simulate its behavior under SPICE. Utilizing a realistic wire model with repeaters, we show that we can break even at median wire length scales of less than 11.5 mm at 0.13 μ and project a break-even point of 2.7 mm for a larger design at 0.07 μ.

Published in:

Software, IEE Proceedings-

Date of Conference:

14-18 Feb. 2004

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