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In this paper, an efficient hardware design for a nonlinear technique for enhancement of color images is presented. The enhancement technique works very effectively for images captured under extremely dark environment as well as non-uniform lighting environment where 'bright" regions are kept unaffected and 'dark' objects in 'bright' background. For efficient implementation of the nonlinear technique on a targeted FPGA board, estimation techniques for logarithm and inverse logarithm are introduced. The estimation method helps to reduce the computational time and FPGA resources significantly compared to conventional implementations of computational intensive operations such as logarithm. The enhancement technique is further analyzed and rearranged into hardware algorithmic steps to better suit the high performance implementation. A number of parallel functional modules are designed to operate simultaneously to optimally utilize the operation-level parallelism available in the technique. Sequential operations are partitioned into well-balance workload stages of a pipelined system based on the inter-data-dependency of the algorithmic steps to better utilize the resources in a FPGA such as on-chip RAM and logic-blocks. The image enhancement system is designed to target the high-performance for real time color image enhancement with minimum 25 frames per second.