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A novel method is presented for implementing the Costas carrier recovery loop for software radio application. This method is fully digital, FPGA-friendly, and process- and resource-efficient. In order to validate the scheme, a Matlab simulation and a hardware description code have been developed. Also, a new procedure has been introduced to generate dynamic test vectors for hardware simulation through Matlab. By application of this method, system and hardware simulators can be coupled. The output of hardware simulation, which includes the effect of quantisation and logic delays, can be evaluated by Matlab. This leads to a realistic performance prediction of the loop. In addition, Verilog code has been synthesised on a specific FPGA to calculate practical resource requirement and maximum achievable frequency.