Skip to Main Content
Data from the test floor has shown that transition faults propagated to all reachable outputs (TARO) is more effective in detecting defective chips compared to conventional transition faults [Tseng et al. 2001]. This paper describes an efficient approach to generate tests pattern based on TARO metric using Boolean satisfiability. The problem of test pattern generation is converted to an instance of Boolean satisfiability and the recent development in the design of efficient SAT solvers has helped to speed up the process of test generation extensively. Experimental results on several benchmarks show the effectiveness of this technique.