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A VLSI architecture for the support of an auditory neural model for hearing and speech processing

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5 Author(s)
Rodellar, V. ; Fac. de Inf., Univ. Politecnica de Madrid, Spain ; Gomez, P. ; Hermida, M. ; Diaz, A.
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A description is given of the VLSI implementation of a signal processor devoted to the support of both an auditory model and a neural model. The first one has been developed as a digital filter, and is able of separating a given speech trace in a set of channels producing a time-frequency representation of speech at a low rate, allowing large savings in computational complexity. The second model implements a phonetic coding scheme for Spanish using a time delay neural network. The signal processor has been designed using serial arithmetics, which allows large savings in area, and may be extended as a systolic system to implement the whole structure. The floorplan of the chip being designed is presented, and provisions for its proper operation as a single device or in an array are also given. The structure described may be used as a phonetic encoder in a connected speech recognition scheme or as a subsystem in hearing aids

Published in:

Circuits and Systems, 1990., Proceedings of the 33rd Midwest Symposium on

Date of Conference:

12-14 Aug 1990