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The data retention time characteristics of the DRAM cell with the negative wordline bias are investigated. With the unique characteristics shown in the gate-induced drain leakage current and the data retention time distribution of the 256-Mb DRAM chip, a model for the sensitivity of data retention time to gate bias is proposed. With the help of two-dimensional device simulation, we found that the relative trap energy (/spl Delta/E/sub t/) of the trap energy to intrinsic Fermi energy plays a key role to determine the retention time of a DRAM cell transistor for the weak cell as well as the normal cell. Also, it is shown the localized trap in the specific region having large electric field is responsible for abnormally large leakage current of the weak cell. An analytic formula for activation energy for the weak cell and the normal cell are also proposed to estimate trap energy level in real device.