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Data retention degradation of a 256-Mbit DRAM during the packaging process is investigated in this paper. Electrical measurement and device simulation show that a trap-assisted leakage degrades the retention time even in packaging process at about 250°C. Retention time of the degraded chip is strongly dependent on the negative wordline voltage and operation temperature, but less sensitive to the substrate bias. Trap-assisted gate induced drain leakage is proposed as the mechanism of retention loss in the degraded chip. The degraded chips usually can be repaired by another thermal baking process. We propose Si-H bond breaking and the subsequent trap generation at the gate and drain overlap region as the root cause of retention degradation according to the fact that the Si-H bond density of backend passivation oxide and nitride layers correlate well with the retention performance of DRAM chips with negative wordline bias. Moreover, the packaged chip shows variable retention behavior during a thermal baking of 250°C. Theoretical calculation indicates that the trap generation or movement to the high electrical field region beneath the gate can increase the trap-assisted gate induced drain leakage by about an order of magnitude.