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A new approach to implement low-power high-performance integrated output pad drivers in monolithic integrated circuits is presented. The design utilizes a source-follower topology along with a simple positive feedback and a simple feed-forward approach to control both rise and fall times for a given loading capacitance. This novel technique is used to implement a differential output pad driver for the high-speed serial data/clock design in a standard 0.13 μm CMOS technology. The driver occupies less than 0.12 mm2 of die area including the area of two ball pads and can drive 50-Ω load through 50-Ω transmission line for higher than 12-Gb/s data rates.
Date of Publication: March 2005