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A 0.35-μm CMOS analog turbo decoder for the 40-bit rate 1/3 UMTS channel code

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6 Author(s)
Vogrig, D. ; Dipt. di Ingegneria dell''Informazione, Univ. di Padova, Italy ; Gerosa, A. ; Neviani, A. ; Graell i Amat, A.
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This work presents the design and the test results of an analog decoder for the 40-bit block length, rate 1/3, Turbo Code defined in the UMTS standard. The prototype is fully integrated in a three-metal double-poly 0.35-μm CMOS technology, and includes an I/O interface that maximizes the decoder throughput. After the successful implementation of proof-of-concept analog iterative decoders by different research groups in both bipolar and CMOS technologies, this is the first reported prototype of an analog decoder for a realistic error-correcting code. The decoder was successfully tested at the maximum data rate defined in the standard (2 Mb/s), with an overall power consumption of 10.3 mW at 3.3 V, going down to 7.6 mW with the decoder core operated at 2 V, and an extremely low energy per decoded bit and trellis state (0.85 nJ for the decoder core alone).

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:40 ,  Issue: 3 )

Date of Publication:

March 2005

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