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Elimination of poly-Si gate depletion for sub-65-nm CMOS technologies by excimer laser annealing

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5 Author(s)
Hiu Yung Wong ; Dept. of Electr. Eng. & Comput. Sci., Univ. of California, Berkeley, CA, USA ; H. Takeuchi ; Tsu-Jae King ; M. Ameen
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Pulsed excimer laser annealing (ELA) is used to reduce the poly-Si gate depletion effect (to <0.1 nm). Low resistivity (0.58 mΩ·cm) and high active boron concentration (4×1020 cm-3) at the gate-oxide interface are achieved while preserving the gate oxide quality and avoiding boron penetration, to meet International Technology Roadmap for Semiconductors requirements for sub-65-nm CMOS technology nodes. ELA is compatible with high-κ dielectric (HfO2) and results in significantly lower gate leakage current density as compared with rapid thermal annealing (RTA).

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IEEE Electron Device Letters  (Volume:26 ,  Issue: 4 )