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This paper presents a novel input test buffer design methodology that is used for testing the differential signaling interconnects. The input test buffer is aimed to detect hardware failures in differential electrical connections. The input test buffer can also be used to check the differential signal's connectivity such as, diagnosing the cable connections, detecting off-lined or un-powered connections. The strategy employed here is to analyze the fault syndromes instead of enumerating the defects to achieve high fault coverage. This analysis leads to defining the key design components comprising of an analog null detector that detects and preserves the fault information in the signal, and several digital engines that process this signal. Preserving the fault information is crucial, as the differential input/output (I/Os) are robust enough to mask the defective signal. The functionality of the test buffer is clearly defined such that the user can customize it to a specific I/O technology. The impact on performance and area are negligible. The proposed input test buffer design was implemented and verified in designs using regular current mode logic (CML) differential input buffers in the 0.13-/spl mu/m process. The results demonstrate comprehensive coverage for catastrophic defects. The fault detection capability is demonstrated through Spice based fault simulations.
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on (Volume:13 , Issue: 3 )
Date of Publication: March 2005