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This work presents the design and modeling of highspeed circuits. Modeling of high-speed circuits is usually divided into physical and behavioral representations. Physical modeling is the actual transistor level design of the high-speed chip or circuit for inter-chip communications and system level simulations. Behavioral modeling imitates the behavior of the circuit when various input/output conditions are encountered. Behavioral modeling is much faster than transistor level modeling because it does not include all the tiny details of transistors. Rather it focuses on the behavior of the circuit. But more accurate results are obtained from physical modeling because it does include all the tiny details that govern the model functionality. Physical modeling using SPICE gives accurate real life operation but requires a long simulation time. While behavioral modeling using input/output buffer information specification takes less simulation time. ASIC designers are using VHDL/Verilog to perform and test chip design on an FPGA for high volume production.