By Topic

A 2K/8K mode small-area FFT processor for OFDM demodulation of DVB-T receivers

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Chua-Chin Wang ; Dept. of Electr. Eng., National Sun Yat-Sen Univ., Kaohsiung, Taiwan ; Jian-Ming Huang ; Hsian-Chang Cheng

We present a novel implementation for 2K/8K dual-mode FFT (fast Fourier transform) for OFDM (orthogonal frequency division multiplexing) of DVB-T (digital video broadcasting terrestrial) receivers. Besides pipelining the FFT to reduce the area and enhance the data throughput, SDF (single-path delay feedback) butterfly units for radix-2 and radix-4 processing are adopted to resolve the power consumption difficulty and the P&R (place and route) problem. The SRAM is used in the butterfly units to relax the auto-refreshing requirement if DRAM is used such that not only is the dynamic power saved, the timing control is also less stingy. The 2K/8K FFT comprises 5/6 cascaded stages of radix-4 and one stage of radix-2 butterfly units. The proposed design is carried out by 0.35 μm 2P4M CMOS process to verify the high processing 8 MHz rate with power dissipation as low as 535 mW at a 16 MHz system clock.

Published in:

Consumer Electronics, IEEE Transactions on  (Volume:51 ,  Issue: 1 )