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Diversity processing WCDMA cell searcher implementation

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7 Author(s)
Eltawil, A.M. ; California Univ., Los Angeles, CA, USA ; Grayver, E. ; Tarighat, A. ; Frigon, J.F.
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In this paper algorithmic and implementation innovations for a novel diversity processing based WCDMA synchronization system are presented. The system employs a dual antenna front end system and a three stage pipelined synchronization technique to achieve slot, frame and code synchronization. The slot boundary section employs a hybrid matched filter/correlator approach for maximum flexibility and to minimize power consumption. The secondary stage section employs a novel maximum likelihood algorithm to perform frame boundary identification, while the third and final stage shares the RAKE engine correlators to perform code identification. The system was implemented in a 0.18 μm CMOS process with 1 poly and 6 metal layers. The total standard cell count is 28k implemented in 1mm2. The average power consumed over a full frame is 2 mW from a 1.8 V supply.

Published in:

Vehicular Technology Conference, 2004. VTC2004-Fall. 2004 IEEE 60th  (Volume:6 )

Date of Conference:

26-29 Sept. 2004