By Topic

DNA sequence matching processor using FPGA and JAVA interface

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
B. O. Brown ; Dept. of Electr. Eng., California State Polytech. Univ., Pomona, CA, USA ; M. -L. Yin ; Y. Cheng

This study uses an FPGA to perform high-speed DNA sequence matching as an alternative to using general purpose computer CPUs. The FPGA is programmed using the Verilog HDL and interfaced using a graphical user interface programmed in JAVA. Design overviews and details for a small scale design are given as well as plans for larger scale expansion. Encouraging results of the small scale model currently in production are also provided. Results of a successful match and no match are shown.

Published in:

Engineering in Medicine and Biology Society, 2004. IEMBS '04. 26th Annual International Conference of the IEEE  (Volume:2 )

Date of Conference:

1-5 Sept. 2004