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In This work, the analyses and design of a very high speed 6 bit analog to digital converter are presented. In order to trade off conversion speed and power consumption, the ADC is implemented with two six-bit half-flash converters operating in a time interleaved way. Each half-flash converter contains seven comparators, and requires two clock cycles to finalize a conversion cycle. However, the overall converter provides one conversion cycle per clock cycle. The high-speed switched-capacitor comparator used in the flash converters performs the functions of sample-and-hold, subtraction and comparison. The circuit exhibits a spurious-free dynamic range (SFDR) of about 40 dB with a full scale sinusoidal input at 200 MHz. The ADC is fabricated in a 0.13 μm CMOS technology, it occupies 0.075 mm2 and dissipates less then 11 mW.