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A simulation study for very low power 5 GHz CMOS voltage-controlled oscillators and frequency dividers

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3 Author(s)
S. Ayoz ; Dept. of Eng., Cambridge Univ., UK ; I. J. Wassell ; F. Udrea

Capability of a deep sub-micron bulk CMOS process for low power RF applications is investigated. Very low power 5 GHz voltage-controlled oscillator and 2:1 frequency divider simulations are presented using a 0.18 μm bulk CMOS process. The VCO uses NMOS varactors and tunes between 4.9 GHz and 6.1 GHz with a phase noise of 108.5 dBc/Hz at 1 MHz offset while drawing 490 μA from a 1.8 V power supply. The 2:1 frequency divider is operational up to 6.7 GHz with only 100-mV peak input signal level. Divider operates with a 1-V power supply drawing only 670 μA.

Published in:

Semiconductor Conference, 2004. CAS 2004 Proceedings. 2004 International  (Volume:1 )

Date of Conference:

4-6 Oct. 2004