A simulation study for very low power 5 GHz CMOS voltage-controlled oscillators and frequency dividers

Capability of a deep sub-micron bulk CMOS process for low power RF applications is investigated. Very low power 5 GHz voltage-controlled oscillator and 2:1 frequency divider simulations are presented using a 0.18 /spl mu/m bulk CMOS process. The VCO uses NMOS varactors and tunes between 4.9 GHz and 6.1 GHz with a phase noise of 108.5 dBc/Hz at 1 MHz offset while drawing 490 /spl mu/A from a 1.8 V power supply. The 2:1 frequency divider is operational up to 6.7 GHz with only 100-mV peak input signal level. Divider operates with a 1-V power supply drawing only 670 /spl mu/A.