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BitSNAP: dynamic significance compression for a low-energy sensor network asynchronous processor

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3 Author(s)
V. N. Ekanayake ; Comput. Syst. Lab., Cornell Univ., Ithaca, NY, USA ; C. Kelly ; R. Manohar

We present a novel asynchronous processor architecture called BitSNAP that utilizes bit-serial datapaths with dynamic significance compression to yield extremely low-energy consumption. Based on the sensor network asynchronous processor (SNAP) ISA, BitSNAP can reduce datapath energy consumption by 50% over a comparable parallel-word processor, while still providing performance suited for powering low-energy sensor network nodes. In 180 nm CMOS, the processor is expected to run at between 6 and 54 MIPS while consuming 152 pJ/ins at 1.8 V and just 17 pJ/ins at 0.6 V.

Published in:

11th IEEE International Symposium on Asynchronous Circuits and Systems

Date of Conference:

14-16 March 2005