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An asynchronous NOC architecture providing low latency service and its multi-level design framework

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5 Author(s)

The demands of scalable, low latency and power efficient system-on-chip interconnect cannot only be satisfied by point-to-point or shared-bus interconnects. In this paper, we propose a new asynchronous network-on-chip (NOC) architecture which provides low latency transfers. This architecture is implemented as a GALS system, where chip units are built as synchronous islands, connected together using a delay insensitive asynchronous network-on-chip topology. The proposed NOC protocol and its asynchronous implementation are presented as well as the multi-level modeling approach using SystemC language and transaction-level-modeling. Preliminary simulation results show that the asynchronous NOC can offer 5 Gbytes/s throughput in a 0.13 μm CMOS technology.

Published in:

Asynchronous Circuits and Systems, 2005. ASYNC 2005. Proceedings. 11th IEEE International Symposium on

Date of Conference:

14-16 March 2005