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Design of high-performance power-aware asynchronous pipelined circuits in MOS current-mode logic

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2 Author(s)
Tin Wai Kwan ; Dept. of Electron., Carleton Univ., Ottawa, Ont., Canada ; Shams, M.

This paper introduces the implementation of multi-GHz power-aware asynchronous pipelined circuits in MOS current-mode logic (MCML). The C-element and double-edge-triggered flip-flop are implemented in MCML and used in the so-called micropipeline circuits. An input data detector is proposed to put the inactive combinational logic into sleep mode. The effects of different layout techniques on the performance and power dissipation of an MCML FIFO are also investigated. Based on post-layout simulation results in a standard 0.18 μm CMOS technology, an asynchronous MCML four-stage FIFO demonstrates a throughput of 4 GHz while dissipating 3.7 mW. The MCML C-element dissipates up to 4× less power compared to its conventional static counterpart at the same throughput of 1.9 GHz. The asynchronous MCML pipelined four-bit carry-look ahead adder with power-saving mechanism reduces the power dissipation by 32% compared to the one without the power-saving mechanism. The power overhead of the input data detector is only 0.23 mW. The input data detector shuts off the stage power in 2 ns and restores the stage in 150 ps after the presence of the new input.

Published in:

Asynchronous Circuits and Systems, 2005. ASYNC 2005. Proceedings. 11th IEEE International Symposium on

Date of Conference:

14-16 March 2005