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GasP control for domino circuits

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4 Author(s)

We present two novel asynchronous control circuits for domino pipelines. The control circuits are based on GasP circuits, have a minimum cycle time of six gate delays, and compare favorably with previously published control circuits. We present some results from a chip implementation of several 64-bit domino adders in a TSMC CMOS 180 nm process technology.

Published in:

11th IEEE International Symposium on Asynchronous Circuits and Systems

Date of Conference:

14-16 March 2005