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Efficient diminished-1 modulo 2n + 1 multipliers

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4 Author(s)
C. Efstathiou ; Dept. of Informatics, TEI of Athens, Greece ; H. T. Vergos ; G. Dimitrakopoulos ; D. Nikolos

In this work, we propose a new algorithm for designing diminished-1 modulo 2n+1multipliers. The implementation of the proposed algorithm requires n + 3 partial products that are reduced by a tree architecture into two summands, which are finally added by a diminished-1 modulo 2n+1 adder. The proposed multipliers, compared to existing implementations, offer enhanced operation speed and their regular structure allows efficient VLSI implementations.

Published in:

IEEE Transactions on Computers  (Volume:54 ,  Issue: 4 )