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Design and analysis of dual-rail circuits for security applications

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4 Author(s)
Sokolov, D. ; Sch. of Electr. Electron. & Comput. Eng., Newcastle Univ., Newcastle upon Tyne, UK ; Murphy, J. ; Bystrov, A. ; Yakovlev, A.

Dual-rail encoding, return-to-spacer protocol, and hazard-free logic can be used to resist power analysis attacks by making energy consumed per clock cycle independent of processed data. Standard dual-rail logic uses a protocol with a single spacer, e.g., all-zeros, which gives rise to energy balancing problems. We address these problems by incorporating two spacers; the spacers alternate between adjacent clock cycles. This guarantees that all gates switch in every clock cycle regardless of the transmitted data values. To generate these dual-rail circuits, an automated tool has been developed. It is capable of converting synchronous netlists into dual-rail circuits and it is interfaced to industry CAD tools. Dual-rail and single-rail benchmarks based upon the advanced encryption standard (AES) have been simulated and compared in order to evaluate the method and the tool.

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Computers, IEEE Transactions on  (Volume:54 ,  Issue: 4 )