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An automatic technique for optimizing Reed-Solomon codes to improve fault tolerance in memories

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3 Author(s)
G. Neuberger ; Fed. Univ. of Rio Grande do Sul, Brazil ; F. G. de Lima Kastensmidt ; R. Reis

Modern SoC architectures manufactured at ever-decreasing geometries use multiple embedded memories. Error detection and correction codes are becoming increasingly important to improve the fault tolerance of embedded memories. This article focuses on automatically optimizing classical Reed-Solomon codes by selecting the appropriate code polynomial and set of used symbols.

Published in:

IEEE Design & Test of Computers  (Volume:22 ,  Issue: 1 )