An average low offset comparator for 1.25 Gsample/s ADC in 0.18 /spl mu/m CMOS

High speed comparators designed using small input transistors exhibit large offsets that affect the dynamic performance of the A/D converter. In this paper, a chopped comparator design is illustrated that uses minimum size input transistors to enable speeds up to 1.25 Gsample/s in a TSMC 0.18 /spl mu/m CMOS process. Chopping at the inputs of the comparator randomizes its offsets yielding a close-to-zero average offset with only increased white-noise floor. This contributes to the increased dynamic range performance and higher spectral purity at the output of the A/D converter. Chopping is made possible by the use of a new low power, low-cost true binary random number generator instead of the traditional pseudo-random number generators. Power consumption and area are reduced because of relaxed design requirements for the same linearity. The circuit-level simulation results, for a 1 V peak to peak input signal, demonstrate superior performance.