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Accessibility analysis on data flow graph: an approach to design for testability

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3 Author(s)
Chung-Hsing Chen ; Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA ; Wu, C. ; Saab, D.G.

Increasing the accessibility of an internal circuit node is one way to achieve design for testability. An algorithm for accessibility analysis based on a data flow graph (DFG) is presented. Based on this analysis, an approach is proposed for improving total accessibility. This is accomplished by selecting the minimum set of circuit nodes that need to be made accessible to ensure that all other nodes are accessible. A simple modification to the DFG that increases accessibility is presented

Published in:

Computer Design: VLSI in Computers and Processors, 1991. ICCD '91. Proceedings, 1991 IEEE International Conference on

Date of Conference:

14-16 Oct 1991