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Allocation of multiport memory with ports of different type in register transfer level synthesis

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1 Author(s)
Chen, C.-I.H. ; Dept. of Electr. Eng., Wright State Univ., Dayton, OH, USA

At present, there is no efficient synthesis approach for multiport memory synthesis in data path design and only single port memory is considered for register allocation in most synthesis systems. An efficient method, partitioned dependence matrix (PDM), is presented to explore the design space for multiport memory synthesis in which the maximum number of read ports can be same as or different from the maximum number of write ports according to the design constraints. The design generator based on the PDM method was developed and implemented to facilitate the register transfer (RT) level synthesis. The input to the design generator is a behavioral description at the RT level which is viewed as a code sequence. PDM provides the memory mechanism as the output

Published in:

Computer Design: VLSI in Computers and Processors, 1991. ICCD '91. Proceedings, 1991 IEEE International Conference on

Date of Conference:

14-16 Oct 1991

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