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In this paper, we propose an FPGA-based hardware accelerator platform with Xilinx Virtex-II V3000 in a compact PCMCIA form factor. By partitioning the complex algorithms in the 4G simulator to the hardware accelerator, we apply an efficient Catapult-C methodology to quickly evaluate the area/speed tradeoffs and rapidly schedule synthesizable RTL models for implementation. The simulation time is accelerated by 100× for a QRD-M algorithm. This not only enables much faster verification in the 4G standard environment, but also provides software/hardware codesign and rapid prototyping of the core algorithm in a realistic fixed-point platform.
Signals, Systems and Computers, 2004. Conference Record of the Thirty-Eighth Asilomar Conference on (Volume:1 )
Date of Conference: 7-10 Nov. 2004