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We have newly developed -surface strained-silicon-on-insulator (SOI) n- and p-MOSFETs on -surface relaxed-SiGe-on-insulator substrates with the Ge content of 25%, fabricated by applying the Ge condensation technique to SiGe layers grown on -surface SOI wafers. We have demonstrated that the electron and the hole mobility enhancement of -surface strained-SOI devices amounts to 23% and 50%, respectively, against the mobilities of -surface unstrained MOSFETs. As a result, the electron and the hole mobility ratios of -surface strained-SOI MOSFETs to the universal mobility of (100)-surface bulk-MOSFETs increase up to 81% and 203%, respectively. Therefore, the current drive imbalance between n- and p-MOS can be reduced. Moreover, both the electron and the hole mobilities of the -surface strained-SOIs strongly depend on the drain current flow direction, which is qualitatively explained by the anisotropic effective mass characteristics of the carriers on a -surface Si. As a result, the -surface strained-SOI technology with optimization of the current flow directions of n- and p-MOS is promising for realizing higher speed scaled CMOS.