Referenced Items are not available for this document.
In this letter, a new methodology for program versus disturb window characterization on split gate flash cell is presented for the first time. The window can be graphically illustrated in Vwl (word-line)-Vss (source) domain under a given program current. This method can help us understand quantitatively how the window shifts versus bias conditions and find the optimal program condition. The condition obtained by this method can have the largest tolerance for program bias variations. This methodology was successfully implemented in 0.18-μm triple self-aligned (SA3) split-gate cell characterization to provide program condition for 32 M products.
Published in:
Electron Device Letters, IEEE
(Volume:26
,
Issue:
3
)
Date of Publication: March 2005
- Page(s):
- 194 - 196
- ISSN :
- 0741-3106
- INSPEC Accession Number:
- 8335093
- Digital Object Identifier :
- 10.1109/LED.2004.842643
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 28 February 2005
- Issue Date :
- March 2005
- Sponsored by :
- IEEE Electron Devices Society
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