By Topic

Predicated switching - optimizing speculation on EPIC machines

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
S. Pillai ; Cadence Design Syst. Inc., San Jose, CA, USA ; M. F. Jacome

Explicitly parallel instruction computing (EPIC) processors are a very attractive platform for many of today's multimedia and communications applications. In particular, clustered EPIC machines can take aggressive advantage of the available instruction-level parallelism, while maintaining high energy-delay efficiency. However, multicluster machines are more challenging to compile to than centralized machines. In this paper, we propose a novel compiler-directed speculation technique called predicated switching (PS) that can be applied to both centralized and multicluster EPIC machines. The two novel contributions in PS are: 1) a compiler transformation, denoted static single assignment-predicated switching, that leverages required data transfers between clusters for performance gains and 2) a static speculation algorithm to decide which specific kernel operations should actually be speculated in the final code, so as to maximize execution performance on the target processor. Experimental results performed on a representative set of time critical kernels compiled for a number of target machines show that, when compared to "resource-unaware" speculation techniques, PS improves performance with respect to at least one of the baselines in 80% of the cases by up to 38%. Moreover, we show that code size and register pressure are not adversely affected by our technique.

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:24 ,  Issue: 3 )