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Transient analysis of board-level drop response of lead-free chip-scale packages with experimental verifications

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2 Author(s)
Chang-Lin Yeh ; Stress-Reliability Lab., Adv. Semicond. Eng. Inc., Kaohsiung, Taiwan ; Yi-Shao Lai

Through the support excitation scheme, transient structural responses of a board-level chip-scale package subjected to the JEDEC drop test are analyzed using the implicit three-dimensional finite element analysis. Analyzed failure modes of the lead-free solder joints are verified with experimental observations. The effect of drop orientations on the reliability of the test vehicle is also examined.

Published in:

Electronics Packaging Technology Conference, 2004. EPTC 2004. Proceedings of 6th

Date of Conference:

8-10 Dec. 2004

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