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A 2-nW 1.1-V self-biased current reference in CMOS technology

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3 Author(s)
Camacho-Galeano, E.M. ; Electr. Eng. Dept., Fed. Univ. of Santa Catarina, Florianopolis, Brazil ; Galup-Montoro, C. ; Schneider, M.C.

This work presents the design of an ultra-low-power self-biased 400-pA current source. We propose the use of a very simple topology along with a design methodology based on the concept of inversion level. An efficient design methodology has resulted in a cell area around 0.045 mm2 in the AMI 1.5-μm CMOS technology and power consumption around 2 nW for 1.2-V supply. Simulated and experimental results validate the design and show that the current source can operate at supply voltages down to 1.1 V with a good regulation (<6% /V variation of the supply voltage) in a 1.5-μm technology.

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Circuits and Systems II: Express Briefs, IEEE Transactions on  (Volume:52 ,  Issue: 2 )