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A 97mW 110MS/s 12b pipeline ADC implemented in 0.18 μm digital CMOS

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7 Author(s)
T. N. Andersen ; Nordic Semicond., Trondheim, Norway ; A. Briskemyr ; F. Telsto ; J. Bjornsen
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A 12 bit pipeline ADC fabricated in a 0.18 μm pure digital CMOS technology is presented. Its nominal conversion rate is 110 MS/s and the nominal supply voltage is 1.8 V. The effective number of bits is 10.4 when a 10 MHz input signal with 2VP-P signal swing is applied. The occupied silicon area is 0.86 mm2 and the power consumption equals 97 mW. A switched capacitor bias current circuit scales the bias current automatically with the conversion rate, which gives scaleable power consumption and full performance of the ADC from 20 to 140 MS/s.

Published in:

Design, Automation and Test in Europe

Date of Conference:

7-11 March 2005