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A probabilistic collocation method based statistical gate delay model considering process variations and multiple input switching

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4 Author(s)
Kumar, S.Y. ; Arizona Univ., Tucson, AZ, USA ; Jun Li ; Talarico, C. ; Wang, J.

Since the advent of new nanotechnologies, the variability of gate delay due to process variations has become a major concern. This paper proposes a new gate delay model that includes impact from both process variations and multiple input switching. The proposed model uses an orthogonal polynomial based probabilistic collocation method to construct a delay analytical equation from circuit timing performance. From the experimental results, our approach has less that 0.2% error on the mean delay of gates and less than 3% error on the standard deviation.

Published in:

Design, Automation and Test in Europe, 2005. Proceedings

Date of Conference:

7-11 March 2005