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Multithreaded extension to multicluster VLIW processors for embedded applications

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4 Author(s)
Barretta, D. ; Dipt. di Elettronica e Inf., Politecnico di Milano, Italy ; Fornaciari, W. ; Sami, M. ; Bagni, D.

Instruction level parallelism (ILP) extraction for multicluster VLIW processors is a very hard task. In this paper, we propose a retargetable architecture that can exploit ILP and thread level parallelism jointly, thus allowing an easier parallelism extraction and improving the performance with respect to traditional multicluster VLIW processors.

Published in:

Design, Automation and Test in Europe, 2005. Proceedings

Date of Conference:

7-11 March 2005