Power-performance trade-offs in nanometer-scale multi-level caches considering total leakage

In this paper, we investigate the impact of T/sub ox/ and V/sub th/ on power performance trade-offs for on-chip caches. We start by examining the optimization of the various components of a single level cache and then extend this to two level cache systems. In addition to leakage, our studies also account for the dynamic power expended as a result of cache misses. Our results show that one can often reduce overall power by increasing the size of the L2 cache if we only allow one pair of V/sub th//T/sub ox/ in L2. However, if we allow the memory cells and the peripherals to have their own V/sub th/ and T/sub ox/, we show that a two-level cache system with smaller L2s will yield less total leakage. We further show that two V/sub th/ and two T/sub ox/ are sufficient to get close to an optimal solution, and that V/sub th/ is generally a better design knob than T/sub ox/ for leakage optimization, thus it is better to restrict the number of T/sub ox/ rather than V/sub th/ if cost is a concern.