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Design space exploration for dynamically reconfigurable architectures

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2 Author(s)
Miramond, B. ; LaMI, Univ. d''Evry Val d''Essonne, France ; Delosme, J.-M.

By incorporating reconfigurable hardware in embedded system architectures it has become easier to satisfy the performance constraints of demanding applications while lowering system cost. In order to evaluate the performance of a candidate architecture, the nodes (tasks) of the data flow graphs that describe an application must be assigned to the computing resources of the architecture: programmable processors and reconfigurable FPGA, whose run-time reconfiguration capabilities must be exploited. In this paper we present a novel design exploration tool - based on a local search algorithm with global convergence properties - which simultaneously explores choices for computing resources, assignments of nodes to these resources, task schedules on the programmable processors and context definitions for the reconfigurable circuits. The tool finds a solution that minimizes system cost while meeting the performance constraints; more precisely it lets the designer select the quality of the optimization (hence its computing time) and finds accordingly a solution with close-to-minimal cost.

Published in:

Design, Automation and Test in Europe, 2005. Proceedings

Date of Conference:

7-11 March 2005