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A fast concurrent power-thermal model for sub-100 nm digital ICs

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5 Author(s)
J. L. Rossello ; Electron. Technol. Group, Univ. de les Illes Baleares, Palma de Mallorca, Spain ; V. Canals ; S. A. Bota ; A. Keshavarzi
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As technology scales down, the static power is expected to become a significant fraction of the total power. The exponential dependence of static power with the operating temperature makes the thermal profile estimation of high-performance IC a key issue to compute the total power dissipated in the next-generation. In this paper we present accurate and compact analytical models to estimate the static power dissipation and the temperature of operation of CMOS gates. The models are the fundamentals of a performance estimation tool in which numerical procedures are avoided for any computation to set a faster estimation and optimization. The models developed are compared to measurements and SPICE simulations for a 0.12 /spl mu/m technology showing excellent results.

Published in:

Design, Automation and Test in Europe

Date of Conference:

7-11 March 2005