Skip to Main Content
As technology scales down, the static power is expected to become a significant fraction of the total power. The exponential dependence of static power with the operating temperature makes the thermal profile estimation of high-performance IC a key issue to compute the total power dissipated in the next-generation. In this paper we present accurate and compact analytical models to estimate the static power dissipation and the temperature of operation of CMOS gates. The models are the fundamentals of a performance estimation tool in which numerical procedures are avoided for any computation to set a faster estimation and optimization. The models developed are compared to measurements and SPICE simulations for a 0.12 μm technology showing excellent results.
Design, Automation and Test in Europe, 2005. Proceedings
Date of Conference: 7-11 March 2005