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Logic design for on-chip test clock generation - implementation details and impact on delay test quality

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6 Author(s)
Beck, M. ; Infineon Technol. AG, Munich, Germany ; Barondeau, O. ; Kaibel, M. ; Poehl, F.
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This paper addresses delay test for SOC devices with high frequency clock domains. A logic design for on-chip high-speed clock generation, implemented to avoid expensive test equipment, is described in detail. Techniques for on-chip clock generation, meant to reduce test vector count and to increase test quality, are discussed. ATPG results for the proposed techniques are given.

Published in:

Design, Automation and Test in Europe, 2005. Proceedings

Date of Conference:

7-11 March 2005