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The use of synthesizable embedded FPGAs in a reconfigurable systems-on-chip (SoC) provides numerous improvements to ASIC designs due to the added flexibility and improvements in functionality. Such arrays have been proposed earlier by the authors and it was found that, as with all reconfigurable architectures, most of the power and area consumed is in the programmable interconnects mesh. This paper focuses on the design of optimized synthesizable switch-boxes that can be used in reconfigurable coarse-grain architectures. The paper compares different switch-boxes in terms of area, power, delay and mutability and proposes new designs optimized for directional data-flow which are found to provide up to 47% less area and 22% less power with only an increase of 10% in routed wirelength and delays when compared to existing designs.