Scheduled System Maintenance:
On Monday, April 27th, IEEE Xplore will undergo scheduled maintenance from 1:00 PM - 3:00 PM ET (17:00 - 19:00 UTC). No interruption in service is anticipated.
By Topic

An FPGA implementation of a modified version of RED algorithm

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Fereydouni-Forouzandeh, F. ; Dept. of Electr. & Comput. Eng., Concordia Univ., Montreal, Que., Canada ; Mohamed, O.A.

Receiving large number of data packets at different baud rates and different sizes at gateways in very high-speed network routers may lead to a congestion problem and force them to drop some packets. Several algorithms have been developed to control this problem. A random early detection (RED) algorithm is commonly used. In this work, we present an FPGA implementation of a modified version of RED able to run as fast as 10 Gbps. Furthermore, we discuss three enhancements of the RED algorithm leading a better performance suitable for FPGA implementation.

Published in:

Field-Programmable Technology, 2004. Proceedings. 2004 IEEE International Conference on

Date of Conference:

6-8 Dec. 2004