Low FPGA area multiplier blocks for full parallel FIR filters

A new algorithm is presented that synthesises multiplier blocks with the goal of minimising FPGA hardware cost. Comparisons with existing algorithms are made via implementing synthesised blocks as the multiplication hardware of fully-pipelined, full-parallel transposed form FIR filters. Results establish that the classic optimisation goal of minimising adders does not minimise FPGA hardware. Instead, minimising multiplier block logic depth is shown to be the primary factor for low area FPGA implementation. Filters generated using the new algorithm are also shown to consume less FPGA area than equivalents implemented using the distributed arithmetic technique.