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Programmable parallel coprocessor architectures for reconfigurable system-on-chip

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2 Author(s)
J. Williams ; Sch. of ITEE, Queensland Univ., Brisbane, Qld., Australia ; N. Bergmann

We propose a hybrid rSoC parallel processing architecture consisting of a central 32-bit RISC microprocessor interconnected to an array of 8-bit microcontrollers as coprocessing nodes. The central processor runs an embedded Linux operating system, with the coprocessor nodes mapped into a virtual file system, by which they can be controlled and reprogrammed. The hardware and software architectures are detailed, and several useful application contexts are proposed. Supporting theoretical analysis is also presented.

Published in:

Field-Programmable Technology, 2004. Proceedings. 2004 IEEE International Conference on

Date of Conference:

6-8 Dec. 2004