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A low-power silicon on sapphire CMOS optoelectronic receiver using low- and high-threshold devices

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2 Author(s)
A. B. Apsel ; Cornell Univ., Ithaca, NY, USA ; A. G. Andreou

We report on the architecture and experimental characterization of a small-footprint optoelectronic receiver for parallel arrays of optical interconnects. The receiver is designed and fabricated in the 0.5-μm silicon on sapphire CMOS technology. The circuit design exploits the properties of MOS transistors with three different threshold voltages and the insulating substrate to achieve a low-power, high-speed and compact circuit. The design attains a 7-pJ energy per bit transduction cost when operated at 1 Gbit/s data rates.

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IEEE Transactions on Circuits and Systems I: Regular Papers  (Volume:52 ,  Issue: 2 )