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Enhancement of CMOS performance by process-induced stress

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2 Author(s)
Yuhao Luo ; Technol. Dev. Group, Xilinx Inc., San Jose, CA, USA ; Nayak, Deepak K.

A detailed analysis of the process-induced stress during a standard CMOS manufacturing is presented. Dependence of transistor performance on layout is attributed to the combination of stress induced by shallow trench isolation and source/drain (S/D) silicide. Based on the layout sensitivity, the effect of an individual stress component on NMOS and PMOS is identified. The optimization of transistor layout is proposed to improve the CMOS performance.

Published in:

Semiconductor Manufacturing, IEEE Transactions on  (Volume:18 ,  Issue: 1 )

Date of Publication:

Feb. 2005

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