Skip to Main Content
This paper reviews several full adder (FA) designs in single electron technology (SET). In addition to the structure and size already reported for these SET FAs, this paper provides a quantitative and qualitative comparison in terms of delay, power dissipation, and sensitivity to (process) variations - for the first time. This can allow for a better understanding of the advantages and disadvantages of each solution. A new SET FA design, based on capacitive SET threshold logic gates, is described and compared with the other SET FAs.