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Design of an adaptive cache coherence protocol for large scale multiprocessors

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3 Author(s)
Q. Yang ; Dept. of Electr. Eng., Rhode Island Univ., Kingston, RI, USA ; G. Thangadurai ; L. N. Bhuyan

A large scale, cache-based multiprocessor that is interconnected by a hierarchical network such as hierarchical buses or a multistage interconnection network (MIN) is considered. An adaptive cache coherence scheme for the system is proposed based on a hardware approach that handles multiple shared reads efficiently. The new protocol allows multiple copies of a shared data block in the hierarchical network, but minimizes the cache coherence overhead by dynamically partitioning the network into sharing and nonsharing regions based on program behavior. The new cache coherence scheme effectively utilizes the bandwidth of the hierarchical networks and exploits the locality properties of parallel algorithms. Simulation experiments have been carried out to analyze the performance of the new protocol. The simulation results show that the new protocol gives 15% to 30% performance improvement over some existing cache coherence schemes on similar systems for a wide range of workload parameters

Published in:

IEEE Transactions on Parallel and Distributed Systems  (Volume:3 ,  Issue: 3 )